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EPM7160ELI84-20
IC CPLD 160MC 20NS 84PLCC
- 제조업체
- Mfr.부분 #EPM7160ELI84-20
- 패키지 84-LCC (J-Lead)
- 데이터시트
- 재고 있음2787
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사양
| Supplier | Intel |
| Package | Tube |
| Series | MAX® 7000 |
| ProductStatus | Obsolete |
| ProgrammableType | EE PLD |
| DelayTimetpd(1)Max | 20 ns |
| VoltageSupply-Internal | 4.5V ~ 5.5V |
| NumberofLogicElements/Blocks | 10 |
| NumberofMacrocells | 160 |
| NumberofGates | 3200 |
| NumberofI/O | 64 |
| OperatingTemperature | -40°C ~ 85°C (TA) |
| MountingType | Surface Mount |
| Package/Case | 84-LCC (J-Lead) |
개요
Description
The EPM7160ELI84-20 is an Altera (now Intel) MAX 7000A EPLD device. It combines a large array of macrocells with programmable interconnect to implement custom combinational and sequential logic. The “7160” denotes its logic capacity, and the “84” indicates an 84-pin package in the ELI family. The “-20” is the speed grade (faster variant). It is a non-volatile, one-device programmable logic device intended for glue logic, address decoding, state machines, peripheral interfaces, and other control tasks in 5V systems. I/O pins are configurable for various TTL/CMOS-compatible functions, and macrocells typically include D-type flip-flops for sequential logic. Programming is done with Altera’s programming tools (e.g., MAX+PLUS II in older flows or Quartus-based tools) using a suitable programmer. In short, it’s a mid-to-high-density EPLD suitable for implementing custom logic without a microcontroller, in a compact 84-pin package.
Features
EPM7160ELI84-20 is an Altera EPLD (MAX 7000S family) in an 84-pin package. Key features:
- 84-pin ELI package; 5V CMOS I/O, TTL-compatible levels
- Speed grade -20 (approximately 20 ns performance)
- High-density logic: ~1.6k equivalent gates with macrocell-based structure
- Numerous user I/O pins (typical ~60+ usable I/Os) with tri-state outputs
- In-system programmable (ISR) via standard Altera programming tools
- Flexible combinational/sequential logic, suitable for glue logic and complex control
- Uses an external configuration memory to load the design at power-up
Note: exact gate, I/O counts vary by configuration; refer to the official datasheet for precise numbers.
- 84-pin ELI package; 5V CMOS I/O, TTL-compatible levels
- Speed grade -20 (approximately 20 ns performance)
- High-density logic: ~1.6k equivalent gates with macrocell-based structure
- Numerous user I/O pins (typical ~60+ usable I/Os) with tri-state outputs
- In-system programmable (ISR) via standard Altera programming tools
- Flexible combinational/sequential logic, suitable for glue logic and complex control
- Uses an external configuration memory to load the design at power-up
Note: exact gate, I/O counts vary by configuration; refer to the official datasheet for precise numbers.
Package
PLCC-84 — 84-pin Plastic Leaded Chip Carrier package.
Pinout
- Pin count: 84 pins
- Function: Altera EPM7160ELI84-20 is an EPLD/CPLD (EPM7160) device used for programmable logic (glue logic, combinational and sequential logic), containing about 7,160 logic elements.
- Function: Altera EPM7160ELI84-20 is an EPLD/CPLD (EPM7160) device used for programmable logic (glue logic, combinational and sequential logic), containing about 7,160 logic elements.
Manufacturer
- Manufacturer: Altera Corporation (now part of Intel Corporation).
- What kind of company: A semiconductor company that designs and sells programmable logic devices (EPLDs/CPLDs and FPGAs) and related software/IP; originally independent, acquired by Intel in 2015.
- What kind of company: A semiconductor company that designs and sells programmable logic devices (EPLDs/CPLDs and FPGAs) and related software/IP; originally independent, acquired by Intel in 2015.
Equivalent
Exact equivalents aren’t published; this is a 160-macrocell Altera EPLD in an 84-pin ELI package. Closest equivalents are other EPM7160ELI84 devices across different speed grades (e.g., -15, -20, -25). For cross-vendor substitutes, consider CPLDs with ~160 macrocells from Xilinx CoolRunner II or Lattice ispMACH/ispLEOPARD, but verify resources and I/O.
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