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EPM7256EGC192-20
IC CPLD 256MC 20NS 192PGA
- 제조업체
- Mfr.부분 #EPM7256EGC192-20
- 패키지 192-BPGA
- 데이터시트
- 재고 있음2155
100% 원래 &새로운
배송 준비 24 시간
365 일 보장
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사양
| Supplier | Intel |
| Package | Tray |
| Series | MAX® 7000 |
| ProductStatus | Obsolete |
| ProgrammableType | EE PLD |
| DelayTimetpd(1)Max | 20 ns |
| VoltageSupply-Internal | 4.75V ~ 5.25V |
| NumberofLogicElements/Blocks | 16 |
| NumberofMacrocells | 256 |
| NumberofGates | 5000 |
| NumberofI/O | 164 |
| OperatingTemperature | 0°C ~ 70°C (TA) |
| MountingType | Surface Mount |
| Package/Case | 192-BPGA |
개요
Description
The EPM7256EGC192-20 is an Altera (now Intel) EPM CPLD device. It’s a non-volatile, 5V-tolerant programmable logic device intended for glue logic and small control circuits.
Key points:
- Package and speed: 192-pin EGC package; -20 speed grade (typical around 20 ns).
- Logic capacity: about 256 macrocells, suitable for implementing sequential and combinational logic, state machines, and simple interfaces.
- I/O: multiple programmable I/O pins, generally TTL/CMOS compatible; designed for 5V operation in classic EPM parts.
- Configuration: onboard non-volatile memory stores the programmed logic; configuration is loaded at power-up.
- Programming and tools: programmed with Altera programming tools (older generations such as MAX+PLUS II or Quartus, depending on era) using programmers like ByteBlaster or in-system programming.
- Use cases: microcontroller interfacing, glue logic, simple state machines, timing and control logic.
- Notes: this is an older CPLD family; for new designs consider modern CPLDs/FPGAs with updated tooling and availability.
For exact electrical specs and pinout, consult the EPM7256EGC192-20 datasheet.
Key points:
- Package and speed: 192-pin EGC package; -20 speed grade (typical around 20 ns).
- Logic capacity: about 256 macrocells, suitable for implementing sequential and combinational logic, state machines, and simple interfaces.
- I/O: multiple programmable I/O pins, generally TTL/CMOS compatible; designed for 5V operation in classic EPM parts.
- Configuration: onboard non-volatile memory stores the programmed logic; configuration is loaded at power-up.
- Programming and tools: programmed with Altera programming tools (older generations such as MAX+PLUS II or Quartus, depending on era) using programmers like ByteBlaster or in-system programming.
- Use cases: microcontroller interfacing, glue logic, simple state machines, timing and control logic.
- Notes: this is an older CPLD family; for new designs consider modern CPLDs/FPGAs with updated tooling and availability.
For exact electrical specs and pinout, consult the EPM7256EGC192-20 datasheet.
Features
EPM7256EGC192-20 features (concise):
- MAX II family CPLD with ~72 macrocells (EPM7256)
- 192-pin TQFP package (device: EPM7256EGC192-20)
- -20 speed grade (fastest available for this device)
- 3.3V operation; standard I/O via multiple banks and global clock network
- In-system programmable (ISP) via JTAG; configuration from external serial ROM/PROM (e.g., EPCQ/EPCS)
- JTAG boundary-scan for programming and testing
- Dedicated global clock buffers and fast carry chains for arithmetic/logical ops
- Low-power operation; suitable for commercial temperature range
- Single-chip CPLD with configurable logic and I/O
Note: exact I/O counts and tolerance vary by bank/pin; refer to the datasheet for detailed bank I/O standards and voltage ranges.
- MAX II family CPLD with ~72 macrocells (EPM7256)
- 192-pin TQFP package (device: EPM7256EGC192-20)
- -20 speed grade (fastest available for this device)
- 3.3V operation; standard I/O via multiple banks and global clock network
- In-system programmable (ISP) via JTAG; configuration from external serial ROM/PROM (e.g., EPCQ/EPCS)
- JTAG boundary-scan for programming and testing
- Dedicated global clock buffers and fast carry chains for arithmetic/logical ops
- Low-power operation; suitable for commercial temperature range
- Single-chip CPLD with configurable logic and I/O
Note: exact I/O counts and tolerance vary by bank/pin; refer to the datasheet for detailed bank I/O standards and voltage ranges.
Package
192-pin Plastic Quad Flat Pack (PQFP), RoHS-compliant package; speed grade -20.
Pinout
- Pin count: 192 pins (TQFP-192 package).
- Function: An EEPROM-based EPLD from the Altera EPM7256 family (256 macrocell device) used as a programmable logic device for implementing combinational and sequential logic with non-volatile configuration; speed grade -20 ns.
- Function: An EEPROM-based EPLD from the Altera EPM7256 family (256 macrocell device) used as a programmable logic device for implementing combinational and sequential logic with non-volatile configuration; speed grade -20 ns.
Manufacturer
Manufacturer: Altera Corporation (now part of Intel Corporation).
About the company: A semiconductor company that designs and manufactures programmable logic devices, including CPLDs and FPGAs (Altera was acquired by Intel in 2015 and is now under Intel’s Programmable Solutions Group).
About the company: A semiconductor company that designs and manufactures programmable logic devices, including CPLDs and FPGAs (Altera was acquired by Intel in 2015 and is now under Intel’s Programmable Solutions Group).
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